The present application claims priority from German patent application Serial Number DE 101 40 485.9 filed Aug. 17, 2001 and entitled xe2x80x9cMethod and Arrangement for Frequency Generationxe2x80x9d which application is incorporated herein by reference in its entirety.
The present invention relates to a method and an arrangement for generating a target frequency from a basic frequency, in which the target frequency is generated by dividing the frequency of a phased signal of the basic frequency by an output dividing factor, the phase of the phased signal being changed cyclically under the control of a phase clock signal.
To generate a target frequency different from a basic frequency from the basic frequency concerned, it is known for the basic frequency to be divided by means of a frequency divider. If the basic frequency is to be divided in this case by a fractional dividing factor, it is not possible for simple synchronous or asynchronous flip-flop circuits to be used and instead different methods have to be employed. To produce a fractional dividing factor, it is for example known for the basic frequency alternately of a first number of cycles to be divided by a first whole-number dividing factor and of a second number of cycles to be divided by a second whole-number dividing factor. As a function of the ratio between the two dividing factors and between the first number of cycles and second number of cycles it is possible for a fractional dividing factor to be simulated in this way. However, this method does have the disadvantage that the output frequency is constantly hopping between two values which result from the first dividing factor and second dividing factor respectively and the target frequency is obtained only as a mean.
To overcome this disadvantage, it is also known for a fractional dividing factor to be obtained by generating a plurality of input phased signals of the basic frequency which are shifted relative to one another by a given phase shift, for one of these input phased signals to be switched forward by a selector circuit to become a phased signal and for its frequency to be divided by a whole-number dividing factor by means of an output divider, the selector circuit being so controlled by the output signal from the output divider that at each cycle of the output signal from the output divider it selects a different input phased signal and switches it forward to become the phased signal. In this way the switching of the output divider can be advanced or retarded by periods of time shorter that one cycle of the basic frequency, which gives a fractional dividing factor between the output frequency of the output divider and the basic frequency. It is known as well for the selector circuit to be driven in such a way that at each cycle of the target frequency it is not the input phased signal of the next higher or next lower phase that is selected and instead a certain number of next higher or next lower phases are skipped. In this way it is possible to obtain different target frequencies by way of the laws adopted for selecting the input phased signals. However, this method has the disadvantage that only one operation of switching between the input phased signals is possible at each cycle of the target frequency. This means that there is only a limited range of possible target frequencies and dividing factors
The object underlying the present invention is to provide a method and an arrangement of the above kind for generating a target frequency from a basic frequency with which it is possible to obtain a wide range of dividing factors, and particularly fractional dividing factors, between the basic frequency and the target frequency. This method is achieved in accordance with the invention by a method having the features given in claim 1 and by an arrangement having the features given in claim 15.
In accordance with the invention, what is used in this case to generate the phase clock signal is not the output signal from the output divider but the phased signal itself. Because the phased signal has not yet been divided by the output dividing factor, it has more cycles per unit of time and thus provides more opportunities for the phase of the phased signal to be changed. It is for example possible in this way for a phase clock signal to be generated which clocks either at each cycle of the phased signal or only after a given number of cycles of the phase clock signal. Advantageously, a control means can preset in this case after how many cycles of the phased signal a clock pulse of the phase clock signal is to be produced.
To generate the phase clock signal from the phased signal, use may advantageously be made of a switch which switches the phased signal forward to become a phase clock signal and which is controlled by a switching signal. If a switch of this kind is constantly closed, the phase clock signal is the same as the phased signal, as a result of which the phase clock signal generates a clock pulse at each cycle of the phased signal. If the switch is opened for a cycle after every given number of cycles of the phased signal, the frequency of the phased signal can be divided in this way. At the same time it is also conceivable for the switch to be closed after every given number of cycles of the phased signal for a given second number of cycles of the phased signal, thus enlarging the scope for generating different controlling clock signals.
When changing the phase of the phased signal, it is possible for various phase states to be defined, with the phases of the phased signal in the various phase states being spaced apart from one another by a given amount. In particular, the phase states may be so selected in this case that the phases in the various phase states are regularly distributed within the length of one cycle of the basic frequency. To change the phase of the phased signal, the various phase states are set to cyclically one after the other so that the phase of the phased signal is advanced or retarded by a given amount at each change of phase state, depending on the sequence in which the phase states are set to. The amount by which the phase of the phased signal is advanced or retarded is equal to the phase difference between the individual phase states.
However, it is also conceivable in this case for individual phase states in the sequence of phase states which are set to be skipped so that the phase of the phased signal is advanced or retarded by a larger amount at each change of phase state. By acting on the sequence in which the phase states are set to, the number of target frequencies that are achievable can be enlarged in this way.
Advantageously, the sequence in which the phase states are set to, or in other words the pattern of change of the phase of the phased signal, is changed as a function of the phased signal. It this way it is possible to cause the phase of the phased signal to be changed not in a constant pattern but in a changing pattern. Since there can only be a finite number of phase states, there are only a limited number of possible ways of setting the phase states one after another. By means of a setting sequence dependent on the phased signal, it is for example possible on the one hand to cause the phase states to be changed cyclically in one direction alternately from one to the next and on the other for one phase state at a time to be skipped when this is done. However, it is also conceivable in this case for a change to be made between quite a large number of different patterns, in which case the individual patterns may be as desired. In this way it possible for the number of target frequencies achievable to be increased still further, this being achieved in particular even when there are only a small number of phase states or in other words possible ways of changing the phase of the phased signal.
To change the phase of the phased signal, or rather to set its phase state, use may on the one hand be made of known devices for changing the phase of a signal. Advantageously however, the phased signal of adjustable phase is generated from a plurality of input phased signals of the basic frequency, the input phased signals having different phase angles relative to one another. When this is the case, one of these input phased signals can be selected by means of a selector circuit and switched through to become the phased signal. The change in the phase of the phased signal is effected in this case by driving the selector circuit and switching through a given input phased signal.
When changing the phase of the phased signal, allowance is advantageously also made for the logic state that the phased signal will be in after its change as compared with its logic state before the change. If the two logic states in question are different, i.e. if the logic state of the phased signal changes when its phase is changed, this may cause a spurious pulse or glitch because the change in the logic state of the phased signal may affect the phase clock signal, which in turn may cause a further change in the phase of the phased signal. To stop this from happening, the logic state of the phased signal is not changed until the logic state of the phased signal after it has been changed will be the same as its logic state was when it was, as yet, unchanged.
To achieve this, an auxiliary phase circuit may be provided which generates an auxiliary phased signal of the basic frequency. This auxiliary phase circuit is driven in such a way that the phase of the auxiliary phased signal generated by it is in advance of the phase of the phased signal by one increment of the phase clock signal. At a given point in time, the auxiliary phased signal is thus in the logic state that the phased signal will be in after its next change. By comparing the auxiliary phased signal and the phased signal, it is possible for the phase clock signal to be retarded in such a way that a change in the phase of the phased signal does not take place until the change will not cause a change in the logic state of the phased signal. For this purpose, the phase clock signal may for example be switched by a switching function which only switches the phase clock signal through when the auxiliary phased signal is in the same logic state as the phased signal.
The invention is explained in detail below by reference to preferred embodiments and to the accompanying drawings.
These and other objects and features of the present invention will become more fully apparent from the following description and appended claims, or may be learned by the practice of the invention as set forth hereinafter.